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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_OpenLoad2

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_CSTIMING2

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_ILIM2

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_OffState_Leakage

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_ResistiveSwitching2

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_Inductive_Switching2

Bob Davis
Designer40261

Bob Davis

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8 years 1 month

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_Inductive_Switching2

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Description

Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_UnderVoltage_SD

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

Version3.3_on_NCV84160_testbench_OpenLoad_&CSTIMING_ILIM

Kevin Toth
Designer168106

Kevin Toth

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6 years 5 months

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Description

NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds