High Side Driver | PartQuest™ Explore

Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

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ON_NCV84160_testbench_BulbLoad_OldVersion

Kevin Toth
Designer168106

Kevin Toth

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6 years 4 months

165

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Tweaking resistance of zd5 and the parallel switches to eliminate VGate2 starting highNOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------This design models all of the NCV84160 functionality intended for the initial model: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

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Mike Fast Lamp and Light Load Test - Wrap_on_NCV84160_chip_V1p2

Mike Donnelly
Designer19

Mike Donnelly

Member for

10 years 5 months

1,555

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10

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Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

Description

Complete model of the ON Semiconductor NCV84160 High Side Driver with a fix to eliminate false OSOL faults produced by an inductive load when the MOSFET shuts off.------------------------------------------------------------------------NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------V1p2 inserts R_OSOL_fix and D_OSOL_fix to damp out Vout oscillations when the MOSFET is switched off in the presence of an inductive load. The manual edits can generate copies that delete these two components to restore the original functionality (V1p0) or implement an alternative fix (V1p1) using a 2.3K leakage resistance across the MOSFET.V1p2 retains all of these features modeled in NCV84160 V1P0 including: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

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Mike Lamp and Light Load Test - Wrap_on_NCV84160_chip_V1p2

Mike Donnelly
Designer19

Mike Donnelly

Member for

10 years 5 months

1,555

designs

10

groups

Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

Description

Complete model of the ON Semiconductor NCV84160 High Side Driver with a fix to eliminate false OSOL faults produced by an inductive load when the MOSFET shuts off.------------------------------------------------------------------------NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------V1p2 inserts R_OSOL_fix and D_OSOL_fix to damp out Vout oscillations when the MOSFET is switched off in the presence of an inductive load. The manual edits can generate copies that delete these two components to restore the original functionality (V1p0) or implement an alternative fix (V1p1) using a 2.3K leakage resistance across the MOSFET.V1p2 retains all of these features modeled in NCV84160 V1P0 including: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

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Wrap_on_NCV84160_chip_V1p2

Norm
Designer43361

Norm

Member for

8 years

328

designs

2

groups

Description

Complete model of the ON Semiconductor NCV84160 High Side Driver with a fix to eliminate false OSOL faults produced by an inductive load when the MOSFET shuts off.------------------------------------------------------------------------NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds ------------------------------------------------------------------------V1p2 inserts R_OSOL_fix and D_OSOL_fix to damp out Vout oscillations when the MOSFET is switched off in the presence of an inductive load. The manual edits can generate copies that delete these two components to restore the original functionality (V1p0) or implement an alternative fix (V1p1) using a 2.3K leakage resistance across the MOSFET.V1p2 retains all of these features modeled in NCV84160 V1P0 including: 1. Detection and regulation of I_limit and low load hazards. 2. CS follows Iout limited to Iout 3. CS signals fault (hazard) conditions otherwise, 4. CS disconnects from Iout as soon as Vin falls to 0.0. 5. CS timing sets delays from Vin and CSD inputs. 6. Thermal effects deferred to future versions.The model is based on the schematic supplied by Aakash Arora and Kevin Toth. It is embedded within the application schematic from Datasheet Figure 14 using component values provided by Kevin Toth.Revisions from previous versions include: 1. Functionality originally implemented via MUX's is nowimplemented by adding an enable input to the Version 3.2 contributes the following revisions: 2. Logic has been de-glitched by adding small delays where appropriate. 3. Gate drive resistances (pull-down and -up) have are tuned to minimize Vout and Iout ripple.NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds

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Mikes copy of Norm final NCV84160_chip_updated

Mike Donnelly
Designer19

Mike Donnelly

Member for

10 years 5 months

1,555

designs

10

groups

Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

Description

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on_NCV84160_V1p2_testbench_Inductive_load

Norm
Designer43361

Norm

Member for

8 years

328

designs

2

groups

Description

Test Bench for NCV84160 chip model V1p2. See datasheet Figure 14. Application Schematic with inductive load at Z_L.-- During an inductive fly-back event when shutting the device-- off (VIN = 5V-0V), once the current decays to 0 A the output-- voltage will rise back up to 0 V with some ringing which-- causes an Off-State Open Load fault.-- on_ncv84160_V1p2 adds a diode in series with a 2.5k Resistance-- from GND to Vout.dprovides no fix for this problem-- This fix leaves alters the schematic topology but activates-- the 2.5K resistance only when an inductive load drives Vout negative.-------------------------------------------------------------------------------------NOTE: ILoad and Vds limit regulation slows down the simulation noticeably. Test simulations should avoid or minimize the duration of Iload &gt; 12A and Vds -------------------------------------------------------------------------------------

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on_NCV84160_V1p0_testbench_Inductive_load

Norm
Designer43361

Norm

Member for

8 years

328

designs

2

groups

Description

About text formats

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Kevin TothDesigner168106

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Mike DonnellyDesigner19

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Mike DonnellyDesigner19

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Mike DonnellyDesigner19

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Kevin Toth
Designer168106

Kevin Toth
Designer168106

Mike Donnelly
Designer19

Kevin Toth
Designer168106

Mike Donnelly
Designer19

Mike Donnelly
Designer19

Norm
Designer43361

Mike Donnelly
Designer19

Norm
Designer43361

Norm
Designer43361